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isolated sigma-delta modulator ad7400a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2011 analog devices, inc. all rights reserved. features 10 mhz clock rate second-order modulator 16 bits, no missing codes 2 lsb inl typical at 16 bits 1.5 v/c typical offset drift on-board digital isolator on-board reference 250 mv analog input range low power operation: 15.5 ma typical at 5.5 v ?40c to +125c operating range 8-lead surface-mount pdip package with gull wing leads and 16-lead soic package ad7401a , external clock version in 16-lead soic safety and regulatory approvals ul recognition 5000 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 891 v peak applications ac motor controls shunt current monitoring data acquisition systems analog-to-digital and opto-isolator replacements general description the ad7400a 1 is a second-order, - modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on analog devices, inc., i coupler? technology. the ad7400a operates from a 5 v power supply and accepts a differential input signal of 250 mv (320 mv full scale). the analog input is sampled continuously by the analog modulator, eliminating the need for external sample- and-hold circuitry. the input information is contained in the output stream as a density of ones with a data rate of 10 mhz. the original information can be reconstructed with an appropriate digital filter. the serial i/o can use a 5 v or a 3 v supply (v dd2 ). the serial interface is digitally isolated. high speed cmos, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. the part contains an on-chip reference and has an operating temperature range of ?40c to +125c. the ad7400a is offered in an 8-lead surface-mount pdip with gull wing leads and a 16-lead soic package. 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. other patents are pending. functional block diagram v in + v dd1 v dd2 v in ? - adc control logic ad7400a b u f t / h ref update gnd 1 gnd 2 mdat mclkout encode encode decode decode watchdog watchdog update 07077-001 figure 1.
ad7400a rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 insulation and safety-related specifications ............................ 5 regulatory information ............................................................... 5 din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information .................................................................... 13 analog input ............................................................................... 13 differential inputs ...................................................................... 14 current sensing applications ................................................... 14 voltage sensing applications .................................................... 14 digital filter ................................................................................ 15 applications information .............................................................. 17 grounding and layout .............................................................. 17 evaluating the ad7400a performance ................................... 17 insulation lifetime ..................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 1/11rev. a to rev. b changed ul recognition from 3750 v rms to 5000 v rms ....... 1 changes to input-to-output momentary withstand voltage value (table 3) .................................................................................. 5 changed ul recognition from 3750 v rms to 5000 v rms (table 4) ............................................................................................. 5 changes to note 1 (table 4) ............................................................ 5 9/08rev. 0 to rev. a added 16-lead soic ......................................................... universal changes to general description section ...................................... 1 changes to table 1, test conditions/comments column ......... 3 changes to timing specifications table summary ..................... 4 changes to table 4, note 2 .............................................................. 5 added figure 6; renumbered sequentially .................................. 8 changes to terminology section.................................................. 12 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 5/08revision 0: initial version
ad7400a rev. b | page 3 of 20 specifications v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in + = ?200 m v to +200 mv , except where specified , and v in ? = 0 v (single - ended); t a = ?40c to +125c , except where specified ; f mclk = 10 mhz, tested with sinc 3 filter, 256 decimation rate, as defined by verilog code, unless otherwise noted. table 1. y version 1 parameter min typ max unit test conditions/comments static performance resolution 16 bits filter output truncated to 16 bits integral nonlinearity 2 2 12 lsb v in + = 200 m v, t a = ?40c to +125 c 4 16 lsb v in + = 250 m v, t a = ?40c to +85c 4 22 lsb v in + = 250 m v, t a = ?40c to +125c differential nonlinearity 2 0.9 lsb guaranteed no missing codes to 16 bits offset error 2 50 500 v offset drift vs. temperature 1.5 4 v/c ? 40c to +125c offset drift vs. v dd1 120 v/v gain error 2 1.5 mv ?40c to +85c 2 mv ?40c to +125c gain error drift vs. temperature 23 v/c ?40c to + 125c gain error drift vs. v dd1 110 v/v analog input input voltage range ?250 +2 50 mv for specified performance, full range = 320 mv dynamic input current 7 8 a v in + = 400 mv, v in ? = 0 v 9 10 a v in + = 500 mv, v in ? = 0 v 0.5 a v in + = v in ? = 0 v input capacitance 10 pf dynamic specifications v in + = 35 hz signal -to - noise and distortion (sinad) ratio 2 70 78 db v in + = 200 mv 68 78 db v in + = 250 mv signal -to - noise ratio (snr) 73 80 db v in + = 200 m v 72 80 db v in + = 250 mv total harmonic distortion (thd) 2 ?84 db v in + = 200 m v ?82 db v in + = 250 mv peak harmonic or spurious noise (sfdr) 2 ?86 d b v in + = 200 m v ?84 db v in + = 250 mv effective number of bits (enob) 2 11.5 12.5 bits v in + = 200 mv 11 12.5 bits v in + = 250 mv isolation transient immunity 2 25 30 kv/s l ogic outputs output high voltage, v oh v dd2 ? 0.1 v i o = ?200 a output low voltage, v ol 0.4 v i o = +200 a power requirements v dd1 4.5 5.5 v v dd2 3 5.5 v i dd1 3 11 13 ma v dd1 = 5.5 v i dd2 4 4.5 6 ma v dd2 = 5.5 v 3 3.5 ma v dd2 = 3.3 v 1 all voltages are relative to their respective ground. 2 see the terminology section. 3 see figure 15 . 4 see figure 16 .
ad7400a rev. b | page 4 of 20 timing specification s v dd1 = 4.5 v to 5. 5 v, v dd2 = 3 v to 5.5 v, t a = ?40c to +125c , except where specified . 1 table 2. parameter limit at t min , t max unit description f mclkout 2 10 mhz typ master clock output frequ ency 9/11 mhz min/ mhz max master clock output frequency t 1 3 40 ns max data access time after mclk rising edge t 2 3 10 ns min data hold time after mclk rising edge t 3 0.4 t mclkout ns min master clock low time t 4 0.4 t mclkout ns min master clock high time 1 sa mple tested during initial release to ensure compliance. 2 mark space ratio for clock output is 40/60 to 60/40. 3 measured with the load circuit shown in figure 2 and defined as the time required for the output to cross 0.8 v or 2.0 v. 200a i ol 200a i oh +1.6v to output pin c l 25pf 07077-002 figure 2 . load circuit for digital output timing specifications mclkout mdat t 1 t 2 t 4 t 3 07077-003 figure 3 . data timing
ad7400a rev. b | page 5 of 20 insulation and safety-related specifications table 3. parameter symbol value unit conditions input-to-output momentary withstand voltage v iso 5000 min v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.46 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) regulatory information table 4. ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 5000 v rms isolation voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 630 v rms maximum working voltage reinforced insulation per din v vde v 0884-10 (vde v 0884-10):2006-12, 891 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each ad7400a is proof tested by applying an insulation te st voltage 6000 v rms for 1 sec (current leakage detection limit = 15 a). 2 in accordance with din v vde v 0884-10, each ad7400a is proof te sted by applying an insulation test voltage 1671 v peak for 1 sec (partial discharge detection limit = 5 pc).
ad7400a rev. b | page 6 of 20 din v vde v 0884 - 10 (vde v 0884- 10) i n sulation c haracteristics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety da ta is ensured by means of protective circuits. table 5. parameter symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 300 v rms i to iv for rated mains voltage 450 v rms i to ii for rated mains voltage 600 v rms i to ii climatic classification 40/105/21 pollution degre e (din vde 0110, table 1 ) 2 maximum working insulation voltage v iorm 891 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1671 v peak input - to - output test voltage, method a v pr after environmental test subgroup 1 1426 v peak v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc after input and/or safety test subgroup 2/ safety test subgroup 3 1069 v peak v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 6000 v peak safety - limiting values (maximum value allowed in the event of a failure, also see figure 4 ) case temperat ure t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s , v io = 500 v r s >10 9 ? case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side 1 side 2 07077-026 figure 4 . thermal derat ing curve, dependence of safety - limiting values with case temperature per din v vde v 0884 - 10
ad7400a rev. b | page 7 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. all voltages are relative to their respecti ve ground. table 6. parameter rating v dd1 to gnd 1 ?0.3 v to +6.5 v v dd2 to gnd 2 ?0.3 v to +6.5 v analog input voltage to gnd 1 ?0.3 v to v dd1 + 0.3 v output voltage to gnd 2 ?0.3 v to v dd2 + 0.3 v input current to any pin excep t supplies 1 10 ma operating temperature range ?40c to +12 5c storage temperature range ?65c to +150c junction temperature 150c pdip package ja thermal impedance 2 116.8 c/w jc thermal impedance 2 38.9 c/w soic package ja thermal impedance 2 89.2c/w jc thermal impedance 2 55.6c/w resistance (input -to - output), r i-o 10 12 ? capacitance (input -to - output), c i-o 3 1.7 pf typ rohs - compliant tempera ture, soldering reflow 260 (+0)c esd 2.5 kv 1 transient currents of up to 100 ma do not cause scr to latch - up. 2 jedec 2s2p sta ndard board. 3 f = 1 mhz. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above t hose indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7 . maximum continuous working voltage 1 paramete r max unit constraint ac voltage, bipolar waveform 565 v peak 50- year minimum lifetime ac voltage, unipolar waveform 891 v peak maximum csa/vde approved working voltage dc voltage 891 v maximum csa/vde approved working voltage 1 refers to continuou s voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. esd caution
ad7400a rev. b | page 8 of 20 pin configuration and function descripti ons v dd1 1 v in + 2 v in ? 3 gnd 1 4 v dd2 8 mclkout 7 mdat 6 gnd 2 5 ad7400a top view (not to scale) 07077-004 figure 5 . 8 - lead pdi p pin configuration 07077-104 nc = no co nn ect ad7400a top view (not to s ca le) v dd1 v dd 2 v in + v in ? gnd 2 gnd 2 v dd1 gnd 1 1 2 3 nc 4 nc 5 nc mclkout nc 16 15 14 nc 6 7 8 mda t nc 11 10 9 13 12 figure 6 . 16 - lead soic pin configuration table 8 . pin function descriptions pin no. pdip soic mnemonic description 1 1, 7 v dd1 supply voltage, 4.5 v to 5.5 v. this is the suppl y voltage for the isolated side of the ad7400a and is relative to gnd 1 . 2 2 v in + positive analog input. specified range of 250 mv. 3 3 v in ? negative analog input. normally connected to gnd 1 . n/a 4 to 6, 10, 12, 15 nc no connect. 4 8 gnd 1 ground 1. this is the ground reference point for all circuitry on the isolated side. 5 9, 16 gnd 2 ground 2. this is the ground reference point for all circuitry on the nonisolated side. 6 11 mdat serial data output. the single bit modulator output is supplied to this pin as a serial data stream . the bits are clocked out on the rising edge of the mclkout output and are valid on the following mclkout risi ng edge. 7 13 mclkout master clock logic output ( 10 mhz t ypical ) . the bit stream from the modulator is valid on the rising edge of mclkout. 8 14 v dd2 supply voltage, 3 v to 5.5 v. this is the supply voltage for the nonisolated side and is relative to gn d 2 .
ad7400a rev. b | page 9 of 20 typical performance characteristics t a = 25c, using 20 khz brickwall filter, unless otherwise noted. 110 0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1m 10m psrr (db) supply ripple frequency (hz) v dd1 = v dd2 = 5v no decoupling capacitor v ripple = 200mv sine wave on v dd1 07077-005 figure 7 . psrr vs. supply ripple frequency without supply decoupling (1 mhz filter used) 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 4000 3500 3000 2500 2000 1500 1000 500 input frequency (hz) sinad (db) v dd1 = v dd2 = 4.5v v dd1 = v dd2 = 5.5v v dd1 = v dd2 = 5v 07077-006 figure 8 . sinad vs. analog input frequency for various supply voltages frequenc y (khz) (db) 0 ?20 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 0 201816141210 8642 8192 point fft f in = 35hz sinad = 79.6991db thd = ?92.6722db decim a tion b y 256 07077-007 figure 9 . typical fft, 200 mv range (using sinc 3 filter, 256 decimation rate) ?85 ?80 ?75 ?70 ?65 ?60 50 100 150 200 300 250 350 sinad (db) input amplitude (mv) v dd1 = v dd2 = 5v t a = 25c 07077-008 figure 10 . sinad vs. v in code dnl error (lsb) 0.5 ?0.4 ?0.3 ?0.2 0 ?0.1 0.1 0.2 0. 3 0. 4 0 60,000 50,000 40,000 30,000 20,000 10,000 v in + = ?200mv to +200mv v in ? = 0v 07077-009 figure 11 . typical dnl, 200 mv range (using sinc 3 filter, 256 decimation rate) code 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0 60,000 50,000 40,000 30,000 20,000 10,000 v in + = ?200mv to +200mv v in ? = 0v inl error (lsb) 07077-010 figure 12 . typical inl, 200 mv range (using sinc 3 filter, 256 decimation rate)
ad7400a rev. b | page 10 of 20 500 450 400 350 300 250 200 150 100 50 0 ?60 ?40 ?20 0 20 40 60 80 100 120 offset (v) temperature (c) v dd1 = v dd2 = 5v t a = 25c 07077-012 figure 13 . offset drift vs. t emperat ure 07077-032 v dd1 = v dd2 = 4.5v ?0.20 0.20 0.15 ?0.05 0 0.05 0.10 ?0.10 ?0.15 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 temperature (c) gain (%) v dd1 = v dd2 = 5v v dd1 = v dd2 = 5.5v figure 14 . gain error drift vs. temperature for various supply voltages 11.0 10.5 10.0 9.5 9.0 8.5 ?0.33 ?0.21 ?0.09 0.03 0. 15 0.27 0.39 i dd1 (ma) v in dc input voltage (v) ?40c +25c +85c +125c 07077-013 v dd2 = v dd1 = 5v figure 15 . i dd1 vs. v in at various temperatures 3.9 2.5 2.7 2.9 3.1 3.3 3.5 3.7 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 i dd2 (ma) v in dc input voltage (v) ?40c +25c +85c +125c 07077-014 v dd2 = v dd1 = 5v figure 16 . i dd2 vs. v in at various temperatures ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 100 1k 10k 100k 1m 10m cmrr (db) common-mode ripple frequency (hz) 07077-015 figure 17 . cmrr vs. common - mode ripple frequency 1.0 0.8 0.6 0.4 0.2 0 ?0.30 ?0.20 ?0.25 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 v in dc input (v) noise (mv) bandwidth = 100khz 07077-017 figure 18 . rms noise voltage vs. v in dc input
ad7400a rev. b | page 11 of 20 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 temperature (c) mclkout (mhz) v dd1 = v dd2 = 4.5v v dd1 = v dd2 = 5v v dd1 = v dd2 = 5.25v 07077-024 figure 19 . mclkout vs. temperature for various supplies
ad7400a rev. b | page 12 of 20 terminology differential nonlinearity differential nonlinearity is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity integral nonlinearity is the maximum deviation fr om a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are specified negative full scale, ?2 5 0 mv (v in + ? v in ?), code 7169, and sp ecified positive full scale, +25 0 mv (v in + ? v in ?), code 58,366 for the 16 - bit level. offset error offset is the deviation of the midscale code (code 32,768 for the 16 - bit level) from the ideal v in + ? v in ? (that is, 0 v). gain error gain error includes both positive full - scale gain error and negative full - scale gain error. positive full - scale gain error is the deviation of the specif ied positive full - scale code (58,366 for the 16- bit level) from the ideal v in + ? v in ? (+25 0 mv) after the offset error is adjusted out. negative full - scale gain error is the deviation of t he specified negative full - scale code (7169 for the 16- bit level) from the ideal v in + ? v in ? (?25 0 mv) after the offset error is adjusted out. gain error includes reference error. signal -to - noise and distortion (sinad) ratio this ratio is t he measured rat io of signal - to - noise and distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal - to - noise and distortion ratio for an ideal n - bit converter with a sine wave input is given by signal - to - noise and distortion = ( 6.02n + 1.76) db therefore, for a 12 - bit converter, sinad is 74 db. effective number of bits (enob) the enob is defined by enob = ( sinad ? 1.76)/6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7400a , it is defined as 1 6 54 32 v vvvvv thd 22222 log20) db ( ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise i s defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum , but for adcs where the harmonics are buried in the noise floor, it is a noise peak. common - mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at 2 50 mv fr equency, f, to the power of a 25 0 mv p - p sine wave applied to the common - mode voltage of v in + and v in ? of frequency f s as cmrr (db) = 10 log( pf/pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but not the converter linearity. psrr is the maximum change in the specified full - scale (25 0 mv) transition point due to a change in power supply voltage from the nominal value (see figure 7 ). isolation transient immunity the isolati on transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. ( the ad7400a was tested using a transient pulse frequency of 100 khz.)
ad7400a rev. b | page 13 of 20 theory of operation circuit information th e ad7400a isolated - modulator converts an analog inp ut signal into a high speed (10 mhz typ ical ), single - bit data stream; the time average of the single - bit data from the modulator is directly proportional to the input signal. figure 22 shows a typical application circuit where the ad7400a is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an n - bit word. analog input the differential analog input of the ad7400a is implemented with a switched capacitor circuit. this circuit implements a second - order modulator stage that digitizes the input signal into a 1 - bit output stream. the sample clock (mclkout) provid es the clock signal for the conversion process as well as the output data - framing clock. this clock source is internal on the ad7400a . the analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. a digital stream that accurately represents the analog input over time appears at the output of the converter (see figure 20). modul at or output +fs analog input ?fs analog input analog input 07077-019 figure 20 . analog input vs. modulator output a differential signal of 0 v ideally re sults in a stream of 1s and 0s at the mdat output pin. this output is high 50% of the time and low 50% of the time. a differential input of 200 mv produces a stream of 1s and 0 s that are high 81.25% of the time (for a +250 mv input , the output stream is hi gh 89.06% of the time) . a differential in put of ?200 mv produces a stream of 1s and 0s that are high 18.75% of the time (for a ?250 mv input , the output stream is high 10.94% of the time) . a differential input of 320 mv ideally results in a stream of all 1s . this is the absolute full - scale range of the ad7400a , while 25 0 mv is the specified full - scale range, as shown in table 9 . table 9 . analog input range analog input voltage input full - scale range +640 mv positive full scale +320 mv positive typical input range +250 mv positive specified input range +200 mv zero 0 mv negative specified input range ?200 mv negative typical input range ?250 mv negative full scale ?320 mv to reconstruct the original information, this output needs to be digitally filtered and decimated. a sinc 3 filter is recom - mended because this is one order higher than that of th e ad7400a modulator. if a 256 decimation rate is used, the resulting 16 - bit word rate is 39 khz, assuming a 10 mhz internal clock frequency. fi gure 21 shows the transfer function of the ad7400a relative to the 16 - bit output. 65535 53248 specified range analog input adc code 12288 ?320mv ?200mv +200mv +320mv 0 07077-020 fi gure 21 . filtered and decimated 16 - bit transfer characteristic - mod/ encoder input current nonisolated 5v/3v isolated 5v v dd1 r shunt v in + v in ? gnd 1 v dd gnd v dd2 mdat mdat sinc 3 filter* ad7400a mclkout sdat cs sclk mclk gnd 2 decoder decoder + encoder 07077-018 * this filter is implemented with an fpga or dsp. figure 22 . typical application circuit
ad7400a rev. b | page 14 of 20 differential inputs the analog input to the modulator is a switched capacitor design. the analog si gnal is converted into charge by highly linear sampling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 23 . a signal source driving the analog input must be able to provide the charge ont o the sampling capacitors every half mclkout cycle and settle to the required accuracy within the next half cycle. a b 1k? v in ? a b b b 1k? v in + 2pf 2pf a a mclkout 07077-027 figure 23 . analog input equivalent circuit because the ad7400a samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common - mode noise at each input. the amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the ad7400a . when a cap acitive load is switched onto the output of an op amp, the amplitude drops momentarily . the op amp tries to correct the situation and, in the process, hits its slew rate limit. this nonlinear response, which can cause excessive ringing, can lead to distort ion. to remedy the situation, a low - pass rc filter can be connected between the amplifier and the input to the ad7400a . the external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. the recommended circuit configuration for driving the differential inputs to achieve best performance is shown in figure 24 . a capacitor between the two input pins sources or si nks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. the series resistor again isolates any op amp from the current spikes created during the sampling process. recommended values for the resisto rs a nd capacitor are 22 ? and 47 pf, respectively. r v in ? r v in + c ad7400a 07077-028 figure 24 . differential input rc network current sensing applications the ad7400a is ideally suited for current sensing applications where the voltage across a shunt resistor is mon itored. the load current flowing through an external shunt resistor produces a voltage at the input terminals of the ad7400a. the ad7400a provides isolation between the analog input from the current sensing resistor and the digital outputs. by selecting th e appropriate shunt resistor value , a variety of current ranges can be monitored. choosing r sense the shunt resistor values used in conjunction with the ad7400a are determined by the specific application requirements in terms of voltage, current, and pow er. small resistors minimize power dissipation, while low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. the final values chosen are a compromise between low power dissipation and good accurac y. low value resistors have less power dissipated in them, but higher value resistors may be required to u s e the full input range of the adc, thus achieving maximum snr performance. when the peak sense current is known, the voltage range of the ad7400a ( 20 0 mv) is divided by the maximum sense current to yield a suitable shunt value. if the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced, in which case, less of the adc input range is used. using less of the adc input range results in performance that is more susceptible to noise and offset errors because offset errors are fixed and are thus more significant when smaller input ranges are used. r sense must be able to dissipate the i2r power losses. if the power dissipa tion rating of the resistor is exceeded, its value may drift or the resistor may be damaged , resulting in an open circuit. this can result in a differential voltage across the terminals of the ad400a in excess of the absolute maximum ratings (see table 6. ) . if i sense has a large high frequency component, take care to choose a resistor with low inductance. voltage sensing applications the ad7400a can also be used fo r isolated voltage monitoring. for examp le, in m otor c ontrol applic ation s , it can be use d to sense bus voltage. in applications where the voltage being monitored exceeds the specified analog input range of the ad7400a , a voltage divider network can be used to reduce the voltage being monitored to the required range.
ad7400a rev. b | page 15 of 20 digital filter the overall system resolution and throughput rate is deter- mined by the filter selected and the decimation rate used. the higher the decimation rate, the greater the system accuracy, as illustrated in figure 25. however, there is a tradeoff between accuracy and throughput rate and, therefore, higher decimal- tion rates result in lower throughput solutions. a sinc 3 filter is recommended for use with the ad7400a. this filter can be implemented on an fpga or a dsp. ? ? ?? 3 1 1 1 )( ? ? ? ? ? ? ? ? ? ? ? ? z z zh dr where dr is the decimation rate. 80 70 60 50 40 30 20 10 0 90 10 100 1k 1 decimation rate snr (db) sinc 3 sinc 2 sinc 1 07077-025 figure 25. snr vs. decimation rate for different filter types the following verilog code provides an example of a sinc 3 filter implementation on a xilinx? spartan-ii 2.5 v fpga. this code can possibly be compiled for another fpga, such as an altera? device. note that the data is read on the negative clock edge in this case, although it can be read on the positive edge, if preferred. figure 25 shows the effect of using different decimation rates with various filter types. /*`data is read on negative clk edge*/ module dec256sinc24b(mdata1, mclk1, reset, data); input mclk1; /*used to clk filter*/ input reset; /*used to reset filter*/ input mdata1; /*ip data to be filtered*/ output [15:0] data; /*filtered op*/ integer location; integer info_file; reg [23:0] ip_data1; reg [23:0] acc1; reg [23:0] acc2; reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; reg [23:0] diff2; reg [23:0] diff3; reg [23:0] diff1_d; reg [23:0] diff2_d; reg [15:0] data; reg [7:0] word_count; reg word_clk; reg init; /*perform the sinc action*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */ else ip_data1 <= 1; /*accumulator (integrator) perform the accumulation (iir) at the speed of the modulator. mclkout ip_data1 acc1+ acc2+ acc3+ + z + z + z 07077-021 figure 26. accumulator z = one sample delay mclkout = modulators conversion bit rate */ always @ (negedge mclk1 or posedge reset) if (reset) begin /*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin /*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end /*decimation stage (mclkout/ word_clk) */ always @ (posedge mclk1 or posedge reset) if (reset) word_count <= 0; else word_count <= word_count + 1; always @ (word_count) word_clk <= word_count[7];
ad7400a rev. b | page 16 of 20 /*differentiator (including decimation stage) perform the differentiation stage (fir) at a lower speed. + ? + ? z ?1 ? + ? z ?1 z ?1 acc3 diff1 diff2 diff3 w ord_clk 0 7077-022 figure 27. differentiator z = one sample delay word_clk = output word rate */ always @ (posedge word_clk or posedge reset) if(reset) begin acc3_d2 <= 0; diff1_d <= 0; diff2_d <= 0; diff1 <= 0; diff2 <= 0; diff3 <= 0; end else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end /* clock the sinc output into an output register word_clk data diff3 07077-023 figure 28. clocking sinc outp ut into an output register word_clk = output word rate */ always @ (posedge word_clk) begin data[15] <= diff3[23]; data[14] <= diff3[22]; data[13] <= diff3[21]; data[12] <= diff3[20]; data[11] <= diff3[19]; data[10] <= diff3[18]; data[9] <= diff3[17]; data[8] <= diff3[16]; data[7] <= diff3[15]; data[6] <= diff3[14]; data[5] <= diff3[13]; data[4] <= diff3[12]; data[3] <= diff3[11]; data[2] <= diff3[10]; data[1] <= diff3[9]; data[0] <= diff3[8]; end endmodule
ad7400a rev. b | page 17 of 20 application s information grounding and layout supply decoupling with a valu e of 100 nf is strongly recom - mended on both v dd1 and v dd2 . decoupling on one or both v ddx pins does not significantly affect performance. in applications involving high common - mode transients, ensure that board coupling across the isolation barrier is mi nimized. furthermore, the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side. failure to ensure this may cause voltage differentials between pins to exceed the absolute maximum ratings of th e device, thereby leading to latch - up or permanent damage. any decoupling used should be placed as close to the supply pins as possible. series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperat ures. if possible, equalize the source impedance on each analog input to minimize offset. beware of mismatch and thermo couple effects on the analog input pcb tracks to reduce offset drift. evaluating the ad7400a performance an ad7400a evaluation board is available with split ground planes and a board split beneath the ad7400a package to ensure isolation. this board allows access to each pin on the device for evaluation purposes. the evaluation board package includes a fully assembled and tested evaluatio n board, documentation , and software for controlling the board from the pc via the e va l - ced1z . the software also includes a sinc 3 filter implemented on an fpga. the evaluation board is used in conjunction with the eval - ced1z board and can be used as a st andalone board. t he software allows the user to perform ac (fast fourier transform) and dc (histo gram of codes) tests on the ad7400a . the software and documentation are on a cd that ship s with the evaluation board. insulation lifetime all insulation st ructures subjected to sufficient time and/or voltage are vulnerable to breakdown. in addition to the testing performed by the regulatory agencies, analog devices has carried out an extensive set of evaluations to determine the lifetime of the insulation st ructure within the ad7400a . these tests subjected populations of devices to continuous cross - isolation voltages. to accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. the time to failure values of t hese units were recorded and used to calculate acceleration factors. these factors were then used to calculate the time to failure under normal operating conditions. the values shown in table 7 are the lesser of the following tw o values: ? the value that ensures at least a 50 - year lifetime of continuous use. ? the maximum csa/vde approved working voltage. note that the lifetime of the ad7400a varies according to the waveform type imposed across the isolation barrier. the i coupler in sulation structure is stressed differently depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 29, figure 30, and figure 31 illustrate the different iso lation voltage waveforms. 0v rated peak voltage 07077-029 figure 29 . bipolar ac waveform 0v rated peak voltage 07077-030 figure 30 . unipolar ac waveform 0v rated peak voltage 07077-031 figure 31 . dc waveform
ad7400a rev. b | page 18 of 20 outline dimensions note th a t this is a pdi p converted t o smd. controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inches equi v alents for reference on ly and are not appropri a te for use in design. 090507- a 8 1 4 5 0.379 (9.63) 0.375 (9.53) 0.371 (9.43) 0.134 (3.40) 0.130 (3.30) 0.126 (3.20) 0.053 (1.35) 0.051 (1.30) 0.049 (1.25) 0.100 (2.54) ref 0.388 (9.86) 0.380 (9.65) 0.372 (9.45) 0.012 (0.303) 0.008 (0.203) 0.004 (0.103) 0.037 (0.94) 0.035 (0.89) 0.033 (0.84) 0.044 (1. 1 18) 0.040 (1.016) 0.036 (0.915) 0.012 (0.305) 0.010 (0.245) 0.008 (0.203) 0.254 (6.45) 0.250 (6.35) 0.246 (6.25) 0.300 (7.62) ref 0.135 (3.43) ref 0.065 (1.651) ref figure 32 . 8- lead dip style surface mount package, with gull wing leads [pdip_smd] (ns- 8) dimensions shown in inches and (millimeter s) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 33 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimete rs and (inches) ordering guide model 1 temperature range package description package option ad7400aynsz ?40c to +125c 8- lead dip style surface mount package, with gull wing leads (pdip_smd) ns -8 AD7400AYRWZ ? 40c to +12 5c 16- lead standard small outline package (soic_w) rw -16 AD7400AYRWZ- rl ? 40c to +12 5c 16- lead standard small outline package (soic_w) rw -16 eval -ad7400aedz standalone evaluation board eval -ced1z development board 1 z = rohs compliant part.
ad7400a rev. b | page 19 of 20 notes
ad7400a rev. b | page 20 of 20 notes ? 2008 C 2011 analog d evices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07077 -0- 1/11(b)

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